Analysis & Synthesis report for Zadatak1
Sat Aug 01 13:11:58 2020
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. General Register Statistics
  9. Elapsed Time Per Partition
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+---------------------------------+--------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Sat Aug 01 13:11:58 2020      ;
; Quartus II 64-Bit Version       ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name                   ; Zadatak1                                   ;
; Top-level Entity Name           ; main                                       ;
; Family                          ; Cyclone V                                  ;
; Logic utilization (in ALMs)     ; N/A                                        ;
; Total registers                 ; 0                                          ;
; Total pins                      ; 24                                         ;
; Total virtual pins              ; 0                                          ;
; Total block memory bits         ; 0                                          ;
; Total DSP Blocks                ; 0                                          ;
; Total HSSI RX PCSs              ; 0                                          ;
; Total HSSI PMA RX Deserializers ; 0                                          ;
; Total HSSI TX PCSs              ; 0                                          ;
; Total HSSI TX Channels          ; 0                                          ;
; Total PLLs                      ; 0                                          ;
; Total DLLs                      ; 0                                          ;
+---------------------------------+--------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CEBA4F23C7        ;                    ;
; Top-level entity name                                                           ; main               ; Zadatak1           ;
; Family name                                                                     ; Cyclone V          ; Cyclone IV GX      ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; PowerPlay Power Optimization                                                    ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Synthesis Seed                                                                  ; 1                  ; 1                  ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                            ;
+-----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path  ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                 ; Library ;
+-----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
; components/CMP1.bdf               ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/CMP1.bdf               ;         ;
; components/CMP2.bdf               ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/CMP2.bdf               ;         ;
; components/DEC2.bdf               ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/DEC2.bdf               ;         ;
; components/RisingEdge.bdf         ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/RisingEdge.bdf         ;         ;
; components/REG1_CL_INC_DEC_SL.bdf ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/REG1_CL_INC_DEC_SL.bdf ;         ;
; components/REG2_CL_INC_DEC.bdf    ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/REG2_CL_INC_DEC.bdf    ;         ;
; components/REG3_CL_INC_SL.bdf     ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/components/REG3_CL_INC_SL.bdf     ;         ;
; main.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Users/katar/Desktop/Zadatak1 - Postavka/main.bdf                          ;         ;
+-----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Estimate of Logic utilization (ALMs needed) ; 0             ;
;                                             ;               ;
; Combinational ALUT usage for logic          ; 0             ;
;     -- 7 input functions                    ; 0             ;
;     -- 6 input functions                    ; 0             ;
;     -- 5 input functions                    ; 0             ;
;     -- 4 input functions                    ; 0             ;
;     -- <=3 input functions                  ; 0             ;
;                                             ;               ;
; Dedicated logic registers                   ; 0             ;
;                                             ;               ;
; I/O pins                                    ; 24            ;
; Total DSP Blocks                            ; 0             ;
; Maximum fan-out node                        ; LED[9]~output ;
; Maximum fan-out                             ; 1             ;
; Total fan-out                               ; 24            ;
; Average fan-out                             ; 0.50          ;
+---------------------------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                       ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+--------------+
; |main                      ; 0 (0)             ; 0 (0)        ; 0                 ; 0          ; 24   ; 0            ; |main               ; work         ;
+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
    Info: Processing started: Sat Aug 01 13:11:57 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Zadatak1 -c Zadatak1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file components/cmp1.bdf
    Info (12023): Found entity 1: CMP1
Info (12021): Found 1 design units, including 1 entities, in source file components/cmp2.bdf
    Info (12023): Found entity 1: CMP2
Info (12021): Found 1 design units, including 1 entities, in source file components/dec2.bdf
    Info (12023): Found entity 1: DEC2
Info (12021): Found 1 design units, including 1 entities, in source file components/risingedge.bdf
    Info (12023): Found entity 1: RisingEdge
Info (12021): Found 1 design units, including 1 entities, in source file components/reg1_cl_inc_dec_sl.bdf
    Info (12023): Found entity 1: REG1_CL_INC_DEC_SL
Info (12021): Found 1 design units, including 1 entities, in source file components/reg2_cl_inc_dec.bdf
    Info (12023): Found entity 1: REG2_CL_INC_DEC
Info (12021): Found 1 design units, including 1 entities, in source file components/reg3_cl_inc_sl.bdf
    Info (12023): Found entity 1: REG3_CL_INC_SL
Info (12021): Found 1 design units, including 1 entities, in source file main.bdf
    Info (12023): Found entity 1: main
Info (12127): Elaborating entity "main" for the top level hierarchy
Warning (275043): Pin "LED[9..0]" is missing source
Warning (275009): Pin "BTN" not connected
Warning (275009): Pin "SW" not connected
Info (12128): Elaborating entity "CMP1" for hierarchy "CMP1:inst"
Warning (275043): Pin "G" is missing source
Warning (275043): Pin "E" is missing source
Warning (275043): Pin "L" is missing source
Warning (275009): Pin "A" not connected
Warning (275009): Pin "B" not connected
Warning (275009): Pin "Gprev" not connected
Warning (275009): Pin "Eprev" not connected
Warning (275009): Pin "Lprev" not connected
Info (12128): Elaborating entity "CMP2" for hierarchy "CMP2:inst1"
Warning (275043): Pin "G" is missing source
Warning (275043): Pin "E" is missing source
Warning (275043): Pin "L" is missing source
Warning (275009): Pin "A" not connected
Warning (275009): Pin "B" not connected
Warning (275008): Primitive "VCC" of instance "inst" not used
Warning (275008): Primitive "GND" of instance "inst1" not used
Info (12128): Elaborating entity "DEC2" for hierarchy "DEC2:inst2"
Warning (275043): Pin "D0" is missing source
Warning (275043): Pin "D1" is missing source
Warning (275043): Pin "D2" is missing source
Warning (275043): Pin "D3" is missing source
Warning (275009): Pin "X1" not connected
Warning (275009): Pin "X0" not connected
Warning (275009): Pin "EN" not connected
Info (12128): Elaborating entity "RisingEdge" for hierarchy "RisingEdge:inst3"
Warning (275043): Pin "y" is missing source
Warning (275009): Pin "x" not connected
Warning (275009): Pin "clk" not connected
Info (12128): Elaborating entity "REG2_CL_INC_DEC" for hierarchy "REG2_CL_INC_DEC:inst4"
Warning (275043): Pin "Q[1..0]" is missing source
Warning (275009): Pin "CL" not connected
Warning (275009): Pin "INC" not connected
Warning (275009): Pin "DEC" not connected
Warning (275009): Pin "clk" not connected
Info (12128): Elaborating entity "REG3_CL_INC_SL" for hierarchy "REG3_CL_INC_SL:inst5"
Warning (275043): Pin "Ci1" is missing source
Warning (275043): Pin "Q[2..0]" is missing source
Warning (275009): Pin "CL" not connected
Warning (275009): Pin "INC" not connected
Warning (275009): Pin "clk" not connected
Warning (275009): Pin "SL" not connected
Warning (275009): Pin "IL" not connected
Warning (275009): Pin "Ci" not connected
Info (12128): Elaborating entity "REG1_CL_INC_DEC_SL" for hierarchy "REG1_CL_INC_DEC_SL:inst7"
Warning (275043): Pin "Qi" is missing source
Warning (275043): Pin "Ci1" is missing source
Warning (275043): Pin "Ei1" is missing source
Warning (275009): Pin "CL" not connected
Warning (275009): Pin "INC" not connected
Warning (275009): Pin "Ci" not connected
Warning (275009): Pin "DEC" not connected
Warning (275009): Pin "Ei" not connected
Warning (275009): Pin "SL" not connected
Warning (275009): Pin "IL" not connected
Warning (275009): Pin "clk" not connected
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LED[9]" is stuck at GND
    Warning (13410): Pin "LED[8]" is stuck at GND
    Warning (13410): Pin "LED[7]" is stuck at GND
    Warning (13410): Pin "LED[6]" is stuck at GND
    Warning (13410): Pin "LED[5]" is stuck at GND
    Warning (13410): Pin "LED[4]" is stuck at GND
    Warning (13410): Pin "LED[3]" is stuck at GND
    Warning (13410): Pin "LED[2]" is stuck at GND
    Warning (13410): Pin "LED[1]" is stuck at GND
    Warning (13410): Pin "LED[0]" is stuck at GND
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 14 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "clk"
    Warning (15610): No output dependent on input pin "BTN[2]"
    Warning (15610): No output dependent on input pin "BTN[1]"
    Warning (15610): No output dependent on input pin "BTN[0]"
    Warning (15610): No output dependent on input pin "SW[9]"
    Warning (15610): No output dependent on input pin "SW[8]"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "SW[6]"
    Warning (15610): No output dependent on input pin "SW[5]"
    Warning (15610): No output dependent on input pin "SW[4]"
    Warning (15610): No output dependent on input pin "SW[3]"
    Warning (15610): No output dependent on input pin "SW[2]"
    Warning (15610): No output dependent on input pin "SW[1]"
    Warning (15610): No output dependent on input pin "SW[0]"
Info (21057): Implemented 24 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 14 input pins
    Info (21059): Implemented 10 output pins
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 78 warnings
    Info: Peak virtual memory: 4660 megabytes
    Info: Processing ended: Sat Aug 01 13:11:58 2020
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


