# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 19:04:28  July 18, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		Zadatak1_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA4F23C7
set_global_assignment -name TOP_LEVEL_ENTITY main
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:04:28  JULY 18, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name BDF_FILE components/CMP1.bdf
set_global_assignment -name BDF_FILE components/CMP2.bdf
set_global_assignment -name BDF_FILE components/DEC2.bdf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name BDF_FILE components/RisingEdge.bdf
set_global_assignment -name BDF_FILE components/REG1_CL_INC_DEC_SL.bdf
set_global_assignment -name BDF_FILE components/REG2_CL_INC_DEC.bdf
set_global_assignment -name BDF_FILE components/REG3_CL_INC_SL.bdf
set_global_assignment -name BDF_FILE main.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_M7 -to BTN[2]
set_location_assignment PIN_W9 -to BTN[1]
set_location_assignment PIN_U7 -to BTN[0]
set_location_assignment PIN_M9 -to clk
set_location_assignment PIN_L1 -to LED[9]
set_location_assignment PIN_L2 -to LED[8]
set_location_assignment PIN_U1 -to LED[7]
set_location_assignment PIN_U2 -to LED[6]
set_location_assignment PIN_N1 -to LED[5]
set_location_assignment PIN_N2 -to LED[4]
set_location_assignment PIN_Y3 -to LED[3]
set_location_assignment PIN_W2 -to LED[2]
set_location_assignment PIN_AA1 -to LED[1]
set_location_assignment PIN_AA2 -to LED[0]
set_location_assignment PIN_AB12 -to SW[9]
set_location_assignment PIN_AB13 -to SW[8]
set_location_assignment PIN_AA13 -to SW[7]
set_location_assignment PIN_AA14 -to SW[6]
set_location_assignment PIN_AB15 -to SW[5]
set_location_assignment PIN_AA15 -to SW[4]
set_location_assignment PIN_T12 -to SW[3]
set_location_assignment PIN_T13 -to SW[2]
set_location_assignment PIN_V13 -to SW[1]
set_location_assignment PIN_U13 -to SW[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top